Digital communication receivers must sample an analog waveform and then reliably detect the sampled data. Signals arriving at a receiver are typically corrupted by intersymbol interference (ISI), crosstalk, echo, and other noise. Thus, receivers typically equalize the channel, to compensate for such distortions, and decode the encoded signals at increasingly high clock rates. Decision-feedback equalization (DFE) is a widely-used technique for removing intersymbol interference and other noise. For a detailed discussion of decision feedback equalizers, see, for example, R. Gitlin et al, Digital Communication Principles, (Plenum Press 1992) and E. A Lee and D. G. Messerschmitt, Digital Communications, (Kluwer Academic Press, 1988), each incorporated by reference herein. Generally, decision-feedback equalization utilizes a nonlinear equalizer to equalize the channel using a feedback loop based on previously decided symbols
Duty cycle distortion is another source of impairment in a received signal. The duty cycle of a clock, for example, is the percentage of time that the clock signal has a given value. A clock should typically demonstrate a 50% duty cycle, such that the clock signal should alternate between two amplitude values, each for 50% of the total duration. Duty cycle distortion arises due to device mismatches and due to variations of the differential signal paths for clock and data The target 50% duty cycle feature is particularly important for high-speed applications where both positive and negative edges are used.
A need exists for improved methods and apparatus for detecting and correcting for impairments in a received signal, such as duty cycle distortion. A further need exists for methods and apparatus that determine the coefficients or thresholds for one or more receiver filters, such as a DFE filter.